The present invention relates to a thin film transistor and method for making the same, and more specifically to a method for fabricating a thin film transistor of the type in which an electrode is placed over a surface formed by a plurality of insulating films.
Thin film transistors (hereinafter referred to as a TFTs) are lightweight, have little thickness, and are advantageous for low power applications. Accordingly, TFTs have been widely used in such products as active matrix type liquid crystal displays (LCDs), organic electroluminescence displays and image sensors.
Various structural modifications have been proposed to further improve the characteristics of TFTs. For example, in a polymer film on array (hereinafter referred to as a PFA) structure, electrically conductive pixel electrodes (made of a material such as indium tin oxide (ITO)) overlap data lines. Such structure prevents electric fields from being applied in a lateral direction to liquid crystal molecules at the ITO electrodes. As a result, disclination lines are confined to data line regions, which may help increase the aperture ratio of the display device.
FIGS. 10(a) to 10(f) show conventional manufacturing process steps for manufacturing a TFT including the above-described PFA structure. As shown in FIG. 10(a), a gate electrode 2 is formed on an insulating substrate 1 of glass composition, for example, by the use of a proper patterning process (a first photo-engraving process; hereinafter referred to as a xe2x80x9cPEPxe2x80x9d). Subsequently, the process advances to a step shown in FIG. 10(b) in which a gate insulating film 3 and a semiconductor layer 4 are deposited on the substrate 1 and the gate electrode 2. In FIG. 10(b), a channel protection film 5 is deposited subsequently, and the channel protection film 5 is subjected to patterning by an appropriate patterning process (second PEP).
The process advances to a step shown in FIG. 10(c), in which electrode material such as Al, Mo, Ta and W is deposited. Thereafter, the electrode material is subjected to patterning, thereby forming a source electrode 6 and a drain electrode 7 (third PEP). Thereafter, a passivation layer 8 is deposited on the surface of the resultant structure, and the passivation layer 8 is subjected to patterning as shown in FIG. 10(d) (fourth PEP). Moreover, an interlayer insulating film 9 is coated on the patterned structure and etching is performed as shown in FIG. 10(e), thereby forming an opening 10 for forming a contact hole (fifth PEP).
Furthermore, an ITO film is deposited and the ITO film is subjected to patterning, thus forming a pixel electrode 11 and a contact hole 12 (sixth PEP) as shown in FIG. 10(f). As described above, though the TFT including PFA can increase an aperture ratio of the pixel electrode 11, the excessive patterning process in which the structure for forming the contact hole 12 through PFA is formed is added to all of the steps of manufacturing the TFT. This leads to an increase in cost to manufacture the TFT including PFA.
Various methods have been proposed to solve such a problem until now. For example, Japanese Laid-Open Patent Application No. 10-170951 (1998), describes a method of manufacturing a liquid crystal display including a step for forming a contact hole in an inorganic insulating film. As described, the contact hole is formed in the inorganic insulating film in self-alignment with a contact hole formed in an interlayer insulating film of organic material which is used as a mask. Therefore, the contact hole is formed in the inorganic insulating film without deviating from the contact hole formed in the interlayer insulating film. Specifically, the precise placement of the contact hole is called a self-alignment property, and the self-alignment property of the contact hole is improved by etching the inorganic insulating film by the use of the interlayer insulating film as a resist layer. However, an end of the inorganic insulating film is overetched more inwardly than an inner wall of the contact hole in many cases, thus forming a step interface.
At such step interface, the overlaid pixel electrode jogs, and may even be trimmed down or cut where it crosses the step interface. Consequently, the pixel electrode may exhibit poor electrical contact, and so-called point defects are likely to occur. In order to prevent such cutting of the pixel electrode, a post-baking step may be performed on the interlayer insulating film, which may help to planarize the interface between the interlayer insulating film and the passivation layer. However, such additional process step adds to manufacturing complexity and the cost of manufacturing the TFT. Moreover, the post-baking step requires the organic interlayer insulating film to be heated to a sufficiently high temperature that causes the interlayer insulating film to shrink. As a result, optical properties of the interlayer insulating film may deteriorate.
Further, Japanese Laid-Open Patent Application No. 11-283934 (1998) describes another method of manufacturing a TFT. As described, an opening for a contact hole is formed in an interlayer insulating film. Then a passivation layer is etched in self-alignment with the contact hole in the interlayer insulating film. As described, resistivity through the contact hole and the pixel electrode is decreased. However, a step results between the interlayer insulating film and the passivation layer, which may lead to a point defect at the step. Another problem is that etching of the passivation layer has poor selectivity which may lead to overetch of the underlying drain electrode. Unless etch conditions are perfectly controlled, such overetch may render some drain electrodes inoperative in a large TFT array (e.g. a display).
By contrast to the above-described conventional TFT and methods of manufacturing TFTs, the inventors of the present invention have investigated a novel device and processing method which may reduce defects heretofore resulting from the TFT having a step interface between an interlayer insulating film and a passivation layer.
According to an embodiment of the present invention, the interlayer insulating film is etched more than once. Accordingly, a method is provided for manufacturing a thin film transistor, the thin film transistor having a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, a passivation layer in which a first opening is formed, and an interlayer insulating film over said passivation layer in which a second opening is formed, wherein the first opening is self-aligned to said second opening, and wherein the method comprises flattening an interface between the first opening and the second opening by etching the interlayer insulating film after etching the first opening.
Preferably, the first etching process (by which the first opening is formed in the passivation layer) is performed with etchant containing hydrofluoric acid, while the second etching process (by which the interface is flattened) is preferably performed with an etchant selected from a group consisting of sodium hydroxide, potassium hydroxide, ammonium hydroxide, tetramethyl ammonium hydroxide, tetra-n-butyl ammonium hydroxide, methyl alcohol, ethyl alcohol, isopropyl alcohol, and a mixture made of these materials. Also, preferably, the inner side wall of the first and second openings forming the contact hole includes a derivative of the basic etchant. Moreover, the TFT of the present invention can preferably be constructed as a bottom gate type TFT or a top gate type TFT.
Preferably, the first etching process can use an acid etchant, and the second etching process can use a basic etchant or a solvent. Furthermore, the first etching process can preferably use an etchant containing hydrofluoric acid, and the second etching process can preferably use a etchant selected from a group consisting of sodium hydroxide, potassium hydroxide, ammonium hydroxide, tetramethyl ammonium hydroxide, tetra-n-butyl ammonium hydroxide, methyl alcohol, ethyl alcohol, isopropyl alcohol, and a mixture made of these materials. Such method may preferably result in a bottom gate type TFT or a top gate type TFT. Preferably, the interlayer insulating film can be made of photoresist.
A TFT according to an embodiment of the invention includes a gate electrode; a gate insulating film; a semiconductor layer; a source/drain electrode; a passivation layer in which a first opening for forming a contact hole is formed; and an interlayer insulating film extending along the passivation layer, in which a second opening for forming the contact hole is formed, wherein the first and second openings are formed so as to be self-aligned with each other, a conductive layer is deposited on an inner side wall of the contact hole, and the inner side wall is formed by performing a plurality of different etching processes in which the inner side wall of the contact hole has been relatively flattened.
Preferably, the interlayer insulating film is selected from thermoplastic resin, thermosetting resin, photosensitive resin and a mixture of these resins. Preferably, the plurality of different etching processes include a process for etching the interlayer insulating film, a first etching process for etching the passivation layer and a second etching process for smoothing the inner side wall by performing a develop back for the interlayer insulating film. The first etching process may preferably use an acid etchant, and the second etching process can use a basic etchant or a solvent.